edu-inf/lab-rv32i-asm-addresses-memory
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feat(L07): add addresses and memory card

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2026-07-21 17:14:02 +02:00
commit 529e720f5d
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tests/task02_word_ram_tb.sv
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module tb;
logic clk = 0, request = 0, write_enable = 0;
logic [31:0] byte_address = 0, write_data = 0, read_data;
logic aligned, fault;
string trace_file;
word_ram dut (.*);
always #1 clk = ~clk;
task automatic write_word(input logic [31:0] address, input logic [31:0] data);
@(negedge clk); request=1; write_enable=1; byte_address=address; write_data=data;
@(posedge clk); #1;
endtask
initial begin
if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
write_word(0, 32'h11223344); write_word(4, 32'haabbccdd);
@(negedge clk); write_enable=0; byte_address=0; #1;
if (read_data !== 32'h11223344 || !aligned || fault) $fatal(1, "FAIL word0=%h", read_data);
byte_address=4; #1; if (read_data !== 32'haabbccdd) $fatal(1, "FAIL word1=%h", read_data);
byte_address=2; write_enable=1; write_data=32'hffffffff; #1;
if (!fault || aligned) $fatal(1, "FAIL misaligned flags");
@(posedge clk); #1; write_enable=0; byte_address=0; #1;
if (read_data !== 32'h11223344) $fatal(1, "FAIL misaligned modified memory");
$display("PASS task02 word0=11223344 word1=aabbccdd misaligned=1");
$finish;
end
endmodule