user
26 lines
1.0 KiB
Systemverilog
26 lines
1.0 KiB
Systemverilog
module alu_core (
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input logic [31:0] operand_a, operand_b,
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input logic [3:0] operation,
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output logic [31:0] result,
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output logic zero
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);
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localparam logic [3:0] ADD=0, SUB=1, AND_OP=2, OR_OP=3, XOR_OP=4,
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SLL_OP=5, SRL_OP=6, SRA_OP=7, SLT_OP=8, SLTU_OP=9;
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always_comb begin
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unique case (operation)
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ADD: result = operand_a + operand_b;
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SUB: result = operand_a - operand_b;
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AND_OP: result = operand_a & operand_b;
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OR_OP: result = operand_a | operand_b;
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XOR_OP: result = operand_a ^ operand_b;
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SLL_OP: result = operand_a << operand_b[4:0];
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SRL_OP: result = operand_a >> operand_b[4:0];
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SRA_OP: result = $signed(operand_a) >>> operand_b[4:0];
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SLT_OP: result = {31'b0, $signed(operand_a) < $signed(operand_b)};
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SLTU_OP: result = {31'b0, operand_a < operand_b};
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default: result = 32'b0;
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endcase
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end
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assign zero = result == 0;
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endmodule
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