user
38 lines
1.3 KiB
YAML
38 lines
1.3 KiB
YAML
schema: 1
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card: rv32i-asm/L03
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title: Blinker and Synchronous Logic
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steps:
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- id: clock-enable
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task: task01_clock_enable
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action: test
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl test hazard3-sim rv32i-asm L03 1
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board:
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show: [source, clock, reset, counter, enable]
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highlight: [posedge, synchronous-reset, terminal-count]
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question: W którym takcie enable może przyjąć wartość 1?
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evidence: [cycle, counter_before, enable_after]
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- id: counter-divider
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task: task02_counter_blinker
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action: debug
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl debug hazard3-sim rv32i-asm L03 2
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board:
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show: [source, waveform, counter, led]
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highlight: [counter_tap, half_period]
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question: Dlaczego wyższy bit licznika zmienia stan rzadziej?
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evidence: [counter_sequence, led_edges, trace_vcd]
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- id: pattern-rom
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task: task03_pattern_rom
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action: debug
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl debug hazard3-sim rv32i-asm L03 3
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board:
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show: [source, waveform, phase, pattern, led]
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highlight: [rom_index, wraparound]
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question: Jaki wzorzec pojawi się po fazie 7?
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evidence: [phase_sequence, led_sequence, wraparound, trace_vcd]
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