user
34 lines
934 B
Systemverilog
34 lines
934 B
Systemverilog
module tb;
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logic clk = 0;
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logic rst = 1;
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logic enable;
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logic [1:0] count;
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integer pulses = 0;
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integer consecutive = 0;
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logic previous = 0;
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string trace_file;
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clock_enable dut (.*);
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always #1 clk = ~clk;
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin
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$dumpfile(trace_file);
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$dumpvars(0, tb);
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end
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repeat (2) @(posedge clk);
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@(negedge clk);
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rst = 0;
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repeat (16) begin
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@(posedge clk); #1;
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if (enable) pulses += 1;
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if (enable && previous) consecutive += 1;
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previous = enable;
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end
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if (pulses != 4 || consecutive != 0 || count != 0)
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$fatal(1, "FAIL task01 pulses=%0d consecutive=%0d count=%0d", pulses, consecutive, count);
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$display("PASS task01 pulses=4 consecutive=0 final_count=0");
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$finish;
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end
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endmodule
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