user
37 lines
1.1 KiB
Systemverilog
37 lines
1.1 KiB
Systemverilog
module tb;
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logic clk = 0;
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logic rst = 1;
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logic led;
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logic [3:0] count;
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integer edge_count = 0;
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integer expected_edges [0:3] = '{4, 8, 12, 16};
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logic previous = 0;
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string trace_file;
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counter_blinker dut (.*);
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always #1 clk = ~clk;
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin
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$dumpfile(trace_file);
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$dumpvars(0, tb);
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end
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repeat (2) @(posedge clk);
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@(negedge clk);
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rst = 0;
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for (integer cycle = 1; cycle <= 16; cycle += 1) begin
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@(posedge clk); #1;
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if (led != previous) begin
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if (cycle != expected_edges[edge_count])
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$fatal(1, "FAIL task02 edge=%0d cycle=%0d", edge_count, cycle);
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edge_count += 1;
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end
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if (led != count[2]) $fatal(1, "FAIL task02 led/count mismatch");
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previous = led;
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end
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if (edge_count != 4) $fatal(1, "FAIL task02 edge_count=%0d", edge_count);
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$display("PASS task02 led_edges=4,8,12,16 period=8");
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$finish;
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end
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endmodule
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