lab-rv32i-asm-decoder/doc/generated/main.tex

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\begin{document}
\sloppy

\vspace{1.0em}
\noindent{\Large\bfseries Cel karty}\par
\vspace{0.35em}
Uczeń rozkłada instrukcję RV32I na pola, klasyfikuje opcode bez stanów niejawnych i dowodzi inwariantu rejestru x0.

\vspace{0.8em}
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\vspace{0.7em}
\noindent{\Large\bfseries Zakres tasków}\par
\vspace{0.35em}

\vspace{0.55em}
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\textbf{Krok} & \textbf{Numer tasku} & \textbf{Najważniejsza idea} & \textbf{Priorytet} & \textbf{Status} & \textbf{Version} \\ \hline
\texttt{4} & \texttt{Task01} & pola i sign extension & obowiązkowe & opracowane & \texttt{v00.01} \\ \hline
\texttt{4} & \texttt{Task02} & klasy opcode i illegal & obowiązkowe & opracowane & \texttt{v00.01} \\ \hline
\texttt{5} & \texttt{Task03} & bank rejestrów i x0 & obowiązkowe & opracowane & \texttt{v00.01} \\ \hline
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\vspace{0.8em}
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\section{Task01 · Pola instrukcji}
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\begingroup
\scriptsize\ttfamily\color{black!60}\sloppy
\noindent drzewka: \pdftooltip[width=\textwidth]{D1}{RV04.WE01.OG.IP.01 | WE 01: Dekodowanie RV32I. Zaprojektowanie weryfikowalnego front-endu\textCR RV32I. | EN IP WO RV04.01: Uczeń analizuje kodowanie instrukcji. | KW IP WS RV04.01: Pola i\textCR immediate są zgodne z kodowaniem.} \pdftooltip[width=\textwidth]{D2}{RV04.WE01.TECH.I4.01 | WE 01: Dekodowanie RV32I. Zaprojektowanie weryfikowalnego front-endu\textCR RV32I. | EK INF04 RV04.01: Uczeń tworzy dekoder i bank rejestrów. | KW INF04 RV04.01:\textCR Testbenche kończą się PASS i zapisują VCD.}\par
\vspace{0.10em}%
\noindent K1: Zapisz pola przed uruchomieniem testu.\quad D1\par
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\noindent K2: Porównaj model, RTL i VCD.\quad D2\par
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Rozłóż słowo \texttt{0xFFC30293}. Pole immediate ma 12 bitów i jest rozszerzane znakiem z \texttt{instr[31]}, dlatego wynik wynosi -4.
\begin{figure}[H]
  \centering
  \includegraphics[width=0.9\linewidth]{\detokenize{../assets/decoder-path.png}}
  \caption{Instrukcja przechodzi przez ekstrakcję pól i dekoder do banku rejestrów.}
  \label{fig:decoder-path}
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\section{Task02 · Klasy opcode}
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\begingroup
\scriptsize\ttfamily\color{black!60}\sloppy
\noindent drzewka: \pdftooltip[width=\textwidth]{D1}{RV04.WE01.OG.IP.01 | WE 01: Dekodowanie RV32I. Zaprojektowanie weryfikowalnego front-endu\textCR RV32I. | EN IP WO RV04.01: Uczeń analizuje kodowanie instrukcji. | KW IP WS RV04.01: Pola i\textCR immediate są zgodne z kodowaniem.} \pdftooltip[width=\textwidth]{D2}{RV04.WE01.TECH.I4.01 | WE 01: Dekodowanie RV32I. Zaprojektowanie weryfikowalnego front-endu\textCR RV32I. | EK INF04 RV04.01: Uczeń tworzy dekoder i bank rejestrów. | KW INF04 RV04.01:\textCR Testbenche kończą się PASS i zapisują VCD.}\par
\vspace{0.10em}%
\noindent K1: Sprawdź siedem legalnych kodów i bezpieczny default.\quad D1 D2\par
\par\vspace{0.18em}%
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Wyjścia klas są one-hot z wyjątkiem dwóch kodów skoku współdzielących sygnał jump. Domyślna gałąź ustawia illegal i nie włącza żadnej operacji.
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\section{Task03 · Bank rejestrów}
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\begingroup
\scriptsize\ttfamily\color{black!60}\sloppy
\noindent drzewka: \pdftooltip[width=\textwidth]{D1}{RV04.WE01.OG.IP.01 | WE 01: Dekodowanie RV32I. Zaprojektowanie weryfikowalnego front-endu\textCR RV32I. | EN IP WO RV04.01: Uczeń analizuje kodowanie instrukcji. | KW IP WS RV04.01: Pola i\textCR immediate są zgodne z kodowaniem.} \pdftooltip[width=\textwidth]{D2}{RV04.WE01.TECH.I4.01 | WE 01: Dekodowanie RV32I. Zaprojektowanie weryfikowalnego front-endu\textCR RV32I. | EK INF04 RV04.01: Uczeń tworzy dekoder i bank rejestrów. | KW INF04 RV04.01:\textCR Testbenche kończą się PASS i zapisują VCD.}\par
\vspace{0.10em}%
\noindent K1: Zapisz x5, spróbuj zapisać x0 i zmierz oba porty.\quad D1 D2\par
\par\vspace{0.18em}%
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Dwa odczyty są kombinacyjne, zapis następuje na zboczu zegara. Adres zero omija tablicę stanu, więc x0 nie może zostać zmieniony.
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\end{document}