user
38 lines
1.4 KiB
YAML
38 lines
1.4 KiB
YAML
schema: 1
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card: rv32i-asm/L04
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title: The RISC-V ISA and Instruction Decoder
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steps:
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- id: instruction-fields
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task: task01_instruction_fields
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action: debug
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl debug hazard3-sim rv32i-asm L04 1
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board:
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show: [instruction, opcode, rd, rs1, immediate, waveform]
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highlight: [instr-6-0, instr-11-7, instr-19-15, sign-extension]
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question: Dlaczego immediate 0xffc oznacza -4, a nie 4092?
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evidence: [encoding, decoded_fields, signed_immediate, trace_vcd]
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- id: opcode-classes
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task: task02_opcode_decoder
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action: test
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl test hazard3-sim rv32i-asm L04 2
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board:
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show: [opcode, class_outputs, illegal]
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highlight: [one-hot-classification, default-illegal]
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question: Które dwa opcode prowadzą do skoku?
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evidence: [seven_legal_classes, illegal_default]
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- id: register-file
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task: task03_register_file
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action: debug
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl debug hazard3-sim rv32i-asm L04 3
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board:
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show: [write_port, rs1, rs2, rd1, rd2, x0, waveform]
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highlight: [posedge-write, asynchronous-read, x0-hardwired-zero]
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question: Co stanie się po próbie zapisu do rejestru x0?
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evidence: [x5_write_read, x0_ignored, dual_read, trace_vcd]
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