user
23 lines
1.1 KiB
Systemverilog
23 lines
1.1 KiB
Systemverilog
module tb;
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logic [6:0] opcode;
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logic alu_imm, alu_reg, load, store, branch, jump, illegal;
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integer legal = 0;
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string trace_file;
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opcode_decoder dut (.*);
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task automatic check_opcode(input logic [6:0] value, input logic [5:0] selected);
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opcode = value; #1;
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if ({jump, branch, store, load, alu_reg, alu_imm} != selected || illegal)
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$fatal(1, "FAIL task02 opcode=%h selected=%b illegal=%b", opcode, {jump, branch, store, load, alu_reg, alu_imm}, illegal);
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legal += 1;
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endtask
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
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check_opcode(7'h13, 6'b000001); check_opcode(7'h33, 6'b000010); check_opcode(7'h03, 6'b000100);
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check_opcode(7'h23, 6'b001000); check_opcode(7'h63, 6'b010000); check_opcode(7'h6f, 6'b100000); check_opcode(7'h67, 6'b100000);
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opcode = 7'h7f; #1;
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if (!illegal || {jump, branch, store, load, alu_reg, alu_imm} != 0) $fatal(1, "FAIL task02 illegal default");
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$display("PASS task02 legal=%0d jump_opcodes=6f,67 illegal_7f=1", legal);
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$finish;
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end
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endmodule
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