feat(L01): add number systems and storage card

src/tasks/task01_positional_encoding.sv

@@ -0,0 +1,12 @@
+module positional_encoding(
+  input  logic [7:0] value,
+  output logic [7:0] bits,
+  output logic [3:0] hex_high,
+  output logic [3:0] hex_low,
+  output logic [8:0] weighted_sum
+);
+  assign bits = value;
+  assign hex_high = value[7:4];
+  assign hex_low = value[3:0];
+  assign weighted_sum = {1'b0, value};
+endmodule

src/tasks/task02_extension_shifts.sv

@@ -0,0 +1,13 @@
+module extension_shifts(
+  input  logic [7:0] value,
+  input  logic [2:0] shift,
+  output logic [31:0] zero_extended,
+  output logic [31:0] sign_extended,
+  output logic [31:0] logical_right,
+  output logic [31:0] arithmetic_right
+);
+  assign zero_extended = {24'b0, value};
+  assign sign_extended = {{24{value[7]}}, value};
+  assign logical_right = zero_extended >> shift;
+  assign arithmetic_right = $signed(sign_extended) >>> shift;
+endmodule

src/tasks/task03_little_endian_memory.sv

@@ -0,0 +1,21 @@
+module little_endian_memory(
+  input logic clk, input logic reset, input logic write_enable,
+  input logic [2:0] address, input logic [31:0] write_word,
+  output logic [31:0] read_word,
+  output logic [7:0] byte0, byte1, byte2, byte3
+);
+  logic [7:0] memory [0:7];
+  integer index;
+  always_ff @(posedge clk) begin
+    if (reset) begin
+      for (index = 0; index < 8; index = index + 1) memory[index] <= 8'h00;
+    end else if (write_enable) begin
+      memory[address] <= write_word[7:0];
+      memory[address + 1] <= write_word[15:8];
+      memory[address + 2] <= write_word[23:16];
+      memory[address + 3] <= write_word[31:24];
+    end
+  end
+  assign read_word = {memory[address + 3], memory[address + 2], memory[address + 1], memory[address]};
+  assign byte0 = memory[0]; assign byte1 = memory[1]; assign byte2 = memory[2]; assign byte3 = memory[3];
+endmodule