user
11 lines
602 B
Systemverilog
11 lines
602 B
Systemverilog
module tb;
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logic [7:0] value; logic [2:0] shift; logic [31:0] zero_extended, sign_extended, logical_right, arithmetic_right; string trace_file;
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extension_shifts dut(.*);
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
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value = 8'h80; shift = 3'd1; #1;
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if (zero_extended !== 32'd128 || $signed(sign_extended) !== -128 || logical_right !== 32'd64 || $signed(arithmetic_right) !== -64) $fatal(1, "extension/shift mismatch");
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$display("PASS task02 input=0x80 zext=128 sext=-128 lsr1=64 asr1=-64"); $finish;
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end
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endmodule
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