user
12 lines
730 B
Systemverilog
12 lines
730 B
Systemverilog
module tb;
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logic clk=0, reset, write_enable; logic [2:0] address; logic [31:0] write_word, read_word; logic [7:0] byte0, byte1, byte2, byte3; string trace_file;
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little_endian_memory dut(.*); always #5 clk = ~clk;
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
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reset=1; write_enable=0; address=0; write_word=0; @(posedge clk); #1; reset=0;
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write_word=32'h12345678; write_enable=1; @(posedge clk); #1; write_enable=0;
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if ({byte3,byte2,byte1,byte0} !== 32'h12345678 || read_word !== 32'h12345678) $fatal(1, "little-endian mismatch");
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$display("PASS task03 word=0x12345678 bytes=78,56,34,12 endian=little roundtrip=1"); $finish;
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end
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endmodule
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