chore: preserve FreeRTOS and C series updates

README.md

@@ -5,6 +5,12 @@ Publiczny manifest wspólnego workspace EDU.
 Repo opisuje serie i karty pracy dostępne dla `stemctl`. Nie przechowuje
 tokenów, lokalnych ścieżek użytkownika ani plików roboczych ucznia.
 
+Widoczność karty w katalogu nie jest uprawnieniem do jej wykonania. W
+zarządzanej usłudze nauczyciel uruchamia kartę przez `teactl`, a `stemctl`
+ucznia może otworzyć i wykonać tylko wersję wskazaną bieżącym
+`CardRunGrant`. Bezpośrednie przeglądanie katalogu pozostaje funkcją
+developerską i standalone.
+
 `workspace.json.series` zawiera wyłącznie aktywne serie obsługiwane przez
 `stemctl`. `workspace.json.catalog_subjects` zasila drzewo UI także seriami
 planowanymi, ale nie udostępnia ich poleceniom pobierania. Pozycję można dodać

catalog/console-bash.json

@@ -3,13 +3,13 @@
   "title": "Bash · Console Tools",
   "catalog_only": true,
   "cards": [
-    {"id": "L01", "repo": "lab-console-busybox", "number": "01", "title": "BusyBox — the Swiss Army Knife", "status": "planned"},
+    {"id": "L01", "repo": "lab-console-busybox", "number": "01", "title": "BusyBox — the Swiss Army Knife", "status": "existing"},
-    {"id": "L02", "repo": "lab-console-tmux", "number": "02", "title": "Tmux — sessions, windows and panes", "status": "planned"},
+    {"id": "L02", "repo": "lab-console-tmux", "number": "02", "title": "Tmux — sessions, windows and panes", "status": "existing"},
-    {"id": "L03", "repo": "lab-console-neovim", "number": "03", "title": "Neovim — navigation and editing", "status": "planned"},
+    {"id": "L03", "repo": "lab-console-neovim", "number": "03", "title": "Neovim — navigation and editing", "status": "existing"},
-    {"id": "L04", "repo": "lab-console-git-basics-1", "number": "04", "title": "Git Basics I — status, add and commit", "status": "planned"},
+    {"id": "L04", "repo": "lab-console-git-basics-1", "number": "04", "title": "Git Basics I — status, add and commit", "status": "existing"},
-    {"id": "L05", "repo": "lab-console-git-basics-2", "number": "05", "title": "Git Basics II — log, diff and restore", "status": "planned"},
+    {"id": "L05", "repo": "lab-console-git-basics-2", "number": "05", "title": "Git Basics II — log, diff and restore", "status": "existing"},
-    {"id": "L06", "repo": "lab-console-git-branching-1", "number": "06", "title": "Git Branching I — branch, switch and merge", "status": "planned"},
+    {"id": "L06", "repo": "lab-console-git-branching-1", "number": "06", "title": "Git Branching I — branch, switch and merge", "status": "existing"},
-    {"id": "L07", "repo": "lab-console-git-branching-2", "number": "07", "title": "Git Branching II — rebase and conflicts", "status": "planned"},
+    {"id": "L07", "repo": "lab-console-git-branching-2", "number": "07", "title": "Git Branching II — rebase and conflicts", "status": "existing"},
-    {"id": "L08", "repo": "lab-console-docker", "number": "08", "title": "Docker Fundamentals", "status": "planned"}
+    {"id": "L08", "repo": "lab-console-docker", "number": "08", "title": "Docker Fundamentals", "status": "existing"}
   ]
 }

catalog/freertos-c.json

@@ -3,7 +3,7 @@
   "title": "FreeRTOS C",
   "catalog_only": true,
   "cards": [
-    {"id": "FC01", "repo": "lab-rv32i-freertos-heap4", "number": "01", "title": "heap_1–heap_5 and heap_4 mechanics", "status": "existing"},
+    {"id": "FC01", "repo": "lab-rv32i-freertos-heap4", "number": "01", "title": "heap_4: From Linear Cursor to Reusable Blocks", "status": "existing"},
     {"id": "FC02", "repo": "lab-rv32i-freertos-c-first-task", "number": "02", "title": "First Task, TCB and Task Stack", "status": "existing"},
     {"id": "FC03", "repo": "lab-rv32i-freertos-c-scheduler", "number": "03", "title": "Tick, Scheduler, Priorities and Time Slicing", "status": "existing"},
     {"id": "FC04", "repo": "lab-rv32i-freertos-c-delay-state", "number": "04", "title": "Delay, Blocking and Task States", "status": "existing"},
@@ -14,9 +14,9 @@
     {"id": "FC09", "repo": "lab-rv32i-freertos-c-event-groups", "number": "09", "title": "Event Groups and Multi-event Synchronization", "status": "existing"},
     {"id": "FC10", "repo": "lab-rv32i-freertos-c-notifications", "number": "10", "title": "Direct-to-task Notifications", "status": "existing"},
     {"id": "FC11", "repo": "lab-rv32i-freertos-c-static-allocation", "number": "11", "title": "Static Allocation and Bounded Storage", "status": "existing"},
-    {"id": "FC12", "repo": "lab-rv32i-freertos-c-diagnostics", "number": "12", "title": "Assertions, Hooks, Stack Checks and Runtime Diagnostics", "status": "planned"},
+    {"id": "FC12", "repo": "lab-rv32i-freertos-c-diagnostics", "number": "12", "title": "Assertions, Hooks, Stack Checks and Runtime Diagnostics", "status": "existing"},
-    {"id": "FC13", "repo": "lab-rv32i-freertos-c-uart", "number": "13", "title": "UART Interrupt-to-task Pipeline", "status": "planned"},
+    {"id": "FC13", "repo": "lab-rv32i-freertos-c-uart", "number": "13", "title": "UART Interrupt-to-task Pipeline", "status": "existing"},
-    {"id": "FC14", "repo": "lab-rv32i-freertos-c-gpio-timer", "number": "14", "title": "GPIO, Hardware Timer and Deferred Work", "status": "planned"},
+    {"id": "FC14", "repo": "lab-rv32i-freertos-c-gpio-timer", "number": "14", "title": "GPIO, Hardware Timer and Deferred Work", "status": "existing"},
-    {"id": "FC15", "repo": "lab-rv32i-freertos-c-integration", "number": "15", "title": "Integrated Deterministic FreeRTOS C Application", "status": "planned"}
+    {"id": "FC15", "repo": "lab-rv32i-freertos-c-integration", "number": "15", "title": "Integrated Deterministic FreeRTOS C Application", "status": "existing"}
   ]
 }

catalog/freertos-cpp.json

@@ -3,20 +3,20 @@
   "title": "FreeRTOS C++",
   "catalog_only": true,
   "cards": [
-    {"id": "K02", "repo": "lab-rv32i-freertos-task-stack-vector", "number": "02", "title": "First Task, Stack, Tick, Scheduler and Vector V0", "status": "existing"},
+    {"id": "K02", "repo": "lab-rv32i-freertos-task-stack-vector", "number": "02", "title": "C++ Task<Derived> Wrapper, CRTP and Lifecycle", "status": "existing"},
-    {"id": "K03", "repo": "lab-rv32i-freertos-vector-raii", "number": "03", "title": "Vector V1 — Destructor, Move, Ownership and RAII", "status": "planned"},
+    {"id": "K03", "repo": "lab-rv32i-freertos-vector-raii", "number": "03", "title": "Vector V1 — Destructor, Move, Ownership and RAII", "status": "existing"},
-    {"id": "K04", "repo": "lab-rv32i-freertos-scheduler-states", "number": "04", "title": "Scheduler States, Priorities and Typed Ticks", "status": "planned"},
+    {"id": "K04", "repo": "lab-rv32i-freertos-scheduler-states", "number": "04", "title": "Scheduler States, Priorities and Typed Ticks", "status": "existing"},
-    {"id": "K05", "repo": "lab-rv32i-freertos-heap-models", "number": "05", "title": "C++ Heap Bridge, Heap Models and HeapStats", "status": "planned"},
+    {"id": "K05", "repo": "lab-rv32i-freertos-heap-models", "number": "05", "title": "C++ Heap Bridge, Heap Models and HeapStats", "status": "existing"},
-    {"id": "K06", "repo": "lab-rv32i-freertos-allocator-resource", "number": "06", "title": "MemoryResource and FreeRtosAllocator<T>", "status": "planned"},
+    {"id": "K06", "repo": "lab-rv32i-freertos-allocator-resource", "number": "06", "title": "MemoryResource and FreeRtosAllocator<T>", "status": "existing"},
-    {"id": "K07", "repo": "lab-rv32i-freertos-task-wrapper", "number": "07", "title": "TaskHandle_t, Explicit Start and Static Trampoline", "status": "planned"},
+    {"id": "K07", "repo": "lab-rv32i-freertos-task-wrapper", "number": "07", "title": "TaskHandle_t, Explicit Start and Static Trampoline", "status": "existing"},
-    {"id": "K08", "repo": "lab-rv32i-freertos-static-task", "number": "08", "title": "DynamicTask, StaticTask, Deletion and Lifetime", "status": "planned"},
+    {"id": "K08", "repo": "lab-rv32i-freertos-static-task", "number": "08", "title": "DynamicTask, StaticTask, Deletion and Lifetime", "status": "existing"},
-    {"id": "K09", "repo": "lab-rv32i-freertos-kernel-facade", "number": "09", "title": "Scheduler Facade and Scoped Kernel Guards", "status": "planned"},
+    {"id": "K09", "repo": "lab-rv32i-freertos-kernel-facade", "number": "09", "title": "Scheduler Facade and Scoped Kernel Guards", "status": "existing"},
-    {"id": "K10", "repo": "lab-rv32i-freertos-queue", "number": "10", "title": "Queue<T> and StaticQueue<T, N>", "status": "planned"},
+    {"id": "K10", "repo": "lab-rv32i-freertos-queue", "number": "10", "title": "Queue<T> and StaticQueue<T, N>", "status": "existing"},
-    {"id": "K11", "repo": "lab-rv32i-freertos-mutex", "number": "11", "title": "Mutex, LockGuard and Priority Inheritance", "status": "planned"},
+    {"id": "K11", "repo": "lab-rv32i-freertos-mutex", "number": "11", "title": "Mutex, LockGuard and Priority Inheritance", "status": "existing"},
-    {"id": "K12", "repo": "lab-rv32i-freertos-semaphore-notify", "number": "12", "title": "Semaphores and Task Notifications", "status": "planned"},
+    {"id": "K12", "repo": "lab-rv32i-freertos-semaphore-notify", "number": "12", "title": "Semaphores and Task Notifications", "status": "existing"},
-    {"id": "K13", "repo": "lab-rv32i-freertos-event-group", "number": "13", "title": "EventGroup and Coordinated State", "status": "planned"},
+    {"id": "K13", "repo": "lab-rv32i-freertos-event-group", "number": "13", "title": "EventGroup and Coordinated State", "status": "existing"},
-    {"id": "K14", "repo": "lab-rv32i-freertos-sw-timer", "number": "14", "title": "Software Timer and the Timer Daemon Task", "status": "planned"},
+    {"id": "K14", "repo": "lab-rv32i-freertos-sw-timer", "number": "14", "title": "Software Timer and the Timer Daemon Task", "status": "existing"},
-    {"id": "K15", "repo": "lab-rv32i-freertos-isr-drivers", "number": "15", "title": "Explicit FromISR, UART and GPIO Wrappers", "status": "planned"},
+    {"id": "K15", "repo": "lab-rv32i-freertos-isr-drivers", "number": "15", "title": "Explicit FromISR, UART and GPIO Wrappers", "status": "existing"},
-    {"id": "K16", "repo": "lab-rv32i-freertos-integration", "number": "16", "title": "Integrated Real-time Application and Evidence", "status": "planned"}
+    {"id": "K16", "repo": "lab-rv32i-freertos-integration", "number": "16", "title": "Integrated Real-time Application and Evidence", "status": "existing"}
   ]
 }

catalog/rv32i-asm.json

@@ -3,14 +3,14 @@
   "title": "ASM · RV32I From Blinker to RISC-V",
   "catalog_only": true,
   "cards": [
-    {"id": "L01", "repo": "lab-rv32i-asm-number-systems", "number": "01", "title": "Number Systems and Storage", "status": "planned"},
+    {"id": "L01", "repo": "lab-rv32i-asm-number-systems", "number": "01", "title": "Number Systems and Storage", "status": "existing"},
-    {"id": "L02", "repo": "lab-rv32i-asm-fpga-bringup", "number": "02", "title": "FPGA Bring-up and Programming", "status": "planned"},
+    {"id": "L02", "repo": "lab-rv32i-asm-fpga-bringup", "number": "02", "title": "FPGA Bring-up and Programming", "status": "existing"},
-    {"id": "L03", "repo": "lab-rv32i-asm-blinker", "number": "03", "title": "Blinker and Synchronous Logic", "status": "planned"},
+    {"id": "L03", "repo": "lab-rv32i-asm-blinker", "number": "03", "title": "Blinker and Synchronous Logic", "status": "existing"},
-    {"id": "L04", "repo": "lab-rv32i-asm-decoder", "number": "04", "title": "The RISC-V ISA and Instruction Decoder", "status": "planned"},
+    {"id": "L04", "repo": "lab-rv32i-asm-decoder", "number": "04", "title": "The RISC-V ISA and Instruction Decoder", "status": "existing"},
-    {"id": "L05", "repo": "lab-rv32i-asm-alu", "number": "05", "title": "ALU and the Verilog Assembler", "status": "planned"},
+    {"id": "L05", "repo": "lab-rv32i-asm-alu", "number": "05", "title": "ALU and the Verilog Assembler", "status": "existing"},
-    {"id": "L06", "repo": "lab-rv32i-asm-control-flow", "number": "06", "title": "Control Flow — Jumps and Branches", "status": "planned"},
+    {"id": "L06", "repo": "lab-rv32i-asm-control-flow", "number": "06", "title": "Control Flow — Jumps and Branches", "status": "existing"},
-    {"id": "L07", "repo": "lab-rv32i-asm-addresses-memory", "number": "07", "title": "Addresses and Memory", "status": "planned"},
+    {"id": "L07", "repo": "lab-rv32i-asm-addresses-memory", "number": "07", "title": "Addresses and Memory", "status": "existing"},
-    {"id": "L08", "repo": "lab-rv32i-asm-subroutines-abi", "number": "08", "title": "Subroutines and the RISC-V ABI", "status": "planned"},
+    {"id": "L08", "repo": "lab-rv32i-asm-subroutines-abi", "number": "08", "title": "Subroutines and ABI", "status": "existing"},
-    {"id": "L09", "repo": "lab-rv32i-asm-load-store", "number": "09", "title": "Load and Store", "status": "planned"}
+    {"id": "L09", "repo": "lab-rv32i-asm-load-store", "number": "09", "title": "Load and Store Semantics", "status": "existing"}
   ]
 }

plans/informatyka/c.md

@@ -1,6 +1,6 @@
 # C — Freestanding RV32I and K&R
 
-Status: 8 kart istniejących lub rozpoczętych, 5 planowanych.
+Status: C01–C13 gotowe; seria C zakończona przed rozpoczęciem serii C++.
 
 ```text
 C · Freestanding RV32I and K&R
@@ -23,5 +23,62 @@ RV32I ASM jest osobną serią-prerekwizytem. C01–C03 tworzą przejście z
 freestanding assemblera do środowiska C, ale pozostają kartami serii C,
 ponieważ ich wynikiem jest rozumienie uruchomienia i ABI programu C.
 
+## Układ każdego przykładu: A1–A8
+
+Każdy przykład źródłowy w karcie serii C jest osobnym taskiem i jawnie
+odpowiada na komplet pytań A1–A8:
+
+```text
+A1 CONTEXT      granica systemu i odpowiedzialność przykładu
+A2 STRUCTURE    typy, obiekty, reprezentacja i ownership
+A3 DISPATCH     granica wywołania, callbacku albo ISR
+A4 APPLICATION  konkretne funkcje, dane i inwariant przykładu
+A5 FLOW         kolejność wykonania oraz checkpointy
+A6 STATE        stan, lifetime i przejścia wartości
+A7 RUNTIME      ABI, rejestry, adresy, sekcje ELF i wynik pomiaru
+A8 PATTERNS     nazwana, rzeczywiście wielokrotnego użytku decyzja
+```
+
+A1–A8 jest profilem pytań, a nie nakazem tworzenia ośmiu dekoracyjnych
+diagramów. Każda pozycja ma status `enabled` albo `unavailable`. Widok
+`enabled` musi wnosić odrębny dowód; `unavailable` zawiera konkretny powód.
+Wartościowy opis tekstowy jest pełnoprawnym widokiem. Diagram powstaje tylko
+wtedy, gdy relacja, kolejność lub stan są mniej czytelne w krótkim tekście.
+
+Dla C04–C06 nowe źródło JSON, TeX, HTML i nowy PDF są dodawane obok
+historycznych kart. Oryginalne `doc/main.tex`, PDF-y oraz przykłady w
+`src/tasks/` pozostają niezmienionym materiałem referencyjnym.
+
 Pełne cele C10–C13 i granica roku znajdują się w
 `series/inf/lab-rv32i-c-pointers-arrays/guidelines/year-01-interrupts-to-year-02-freertos.md`.
+
+## Stan odbioru serii C — 2026-07-20
+
+Każda karta ma wygenerowane źródło JSON, widok web i nowy PDF. Odbiór
+potwierdza dokładną kolejność A1–A8 w każdym tasku, jawne uzasadnienie każdego
+N/D, poprawny JSON i JavaScript, poprawność PDF według `qpdf` oraz brak pustych,
+anonimowych i przepełnionych stron. Przykłady uruchamialne przeszły właściwe
+testy hostowe i/lub wyrocznie Hazard3.
+
+```text
+karta  przykłady  bloki A1–A8
+C01           3            24
+C02           4            32
+C03           2            16
+C04          12            96
+C05           8            64
+C06          11            88
+C07          12            96
+C08           4            32
+C09           5            40
+C10           3            24
+C11           3            24
+C12           3            24
+C13           4            32
+RAZEM        74           592
+```
+
+PDF-y mają łącznie 180 stron. Spośród 592 widoków 508 ma stan `enabled`, a 84
+ma stan `unavailable` z konkretnym powodem. Historyczne źródła C04–C06 nadal są
+materiałem referencyjnym: nowy układ nie nadpisuje `doc/main.tex`, starych
+PDF-ów ani przykładów w `src/tasks/`.

plans/informatyka/console-bash.md

@@ -1,6 +1,7 @@
 # Bash · Console Tools — plan kart
 
-Status: plan, 8 lekcji.
+Status: L01–L08 gotowe; seria zakończona i odbierana w profilu
+`native-amd64` przez `stemctl`.
 
 Seria przygotowuje warsztat przed FPGA, assemblerem i C. Nazwa obejmuje pracę
 w powłoce i terminalu; BusyBox może udostępniać `ash`, więc nie utożsamiamy
@@ -18,8 +19,53 @@ Bash · Console Tools
 └── L08 · Docker Fundamentals
 ```
 
-Każda karta kończy się małym dowodem wykonania: komendą, stanem terminala albo
+Każda karta zawiera trzy wykonywalne taski. Repozytorium karty dostarcza
-historią Git, którą uczeń potrafi odtworzyć i wyjaśnić.
+kontrakt `stem-card.yaml`, testy stanu, wygenerowany widok React, dwustronicowy
+PDF A4 oraz akcje `build`, `test`, `run` i `debug`. Debug zapisuje
+`trace.log` w katalogu artefaktów tasku.
+
+## Stan odbioru serii — 2026-07-21
+
+| Karta | Dowód końcowy |
+| --- | --- |
+| L01 BusyBox | dispatch multicall, operacje plikowe, proces i host |
+| L02 Tmux | sesja, okna i panele, zachowanie stanu po detach/attach |
+| L03 Neovim | nawigacja, search/edit/save, undo/redo |
+| L04 Git Basics I | init, status/add, pierwszy commit i clean |
+| L05 Git Basics II | log, diff staged/worktree, bezpieczne restore |
+| L06 Git Branching I | branch/switch, rozbieżność, merge commit |
+| L07 Git Branching II | rebase, rzeczywisty konflikt UU, liniowa historia |
+| L08 Docker | specyfikacja image, lifecycle, volume i bind mount |
+
+Wszystkie 24 taski przechodzą w kontenerze `native-amd64`. Każdy task pracuje
+w izolowanym katalogu tymczasowym i raportuje mierzalny komunikat `PASS`.
+
+### Granice środowiska
+
+Obraz `native-amd64` nie zawiera BusyBox. L01 używa więc audytowalnego
+fixture C implementującego wyłącznie ćwiczony mechanizm multicall, wykrywa
+prawdziwy BusyBox, gdy jest dostępny, i zawsze raportuje użyty backend. Fixture
+nie jest przedstawiany jako binarka BusyBox.
+
+Profil ucznia nie otrzymuje socketu Docker/Podman. L08 używa jawnego modelu
+stanów offline do sprawdzenia semantyki image/container/storage. Jego `PASS`
+nie oznacza uruchomienia prawdziwego silnika. Powtórzenie ćwiczenia z realnym
+CLI należy wykonać na kontrolowanej maszynie operatorskiej, najlepiej z
+rootless Podmanem albo Dockerem, bez montowania socketu do kontenera ucznia.
+
+### Sposób uruchamiania
+
+```bash
+stemctl series show console-bash
+stemctl list-cards console-bash
+stemctl card use console-bash L01
+stemctl test native-amd64 console-bash L01 1
+stemctl debug native-amd64 console-bash L01 3
+```
+
+Numer karty i tasku można podmienić na dowolne L01–L08 i 1–3. Identyfikatory,
+repozytoria i kolejność kart są zapisane w `series/console-bash.json`, a stan
+realizacji w `catalog/console-bash.json`.
 
 Pierwotne ustalenia znajdują się również w
 `series/inf/lab-rv32i-c-pointers-arrays/guidelines/console-series.md`.

plans/informatyka/freertos-c.md

@@ -1,8 +1,8 @@
 # FreeRTOS C — book-led card sequence
 
-Status: FC01–FC02 exist; FC03 is the next implementation; FC04–FC15 are
+Status: FC01–FC15 istnieją; blok 15 kart FreeRTOS C jest kompletny i stanowi
-planned. This series uses only the FreeRTOS C API. C++ wrappers belong to a
+zamknięty fundament przed serią FreeRTOS C++. Każda karta używa publicznego
-later, separate series.
+API C, a końcowa FC15 scala mechanizmy w jeden deterministyczny eksperyment.
 
 ## Primary source and ordering rule
 
@@ -62,7 +62,7 @@ simulator.
 
 ```text
 FreeRTOS C — 15 cards
-├── FC01 · Heap schemes and heap_4 block mechanics
+├── FC01 · heap_4: from a linear cursor to reusable blocks
 ├── FC02 · First task, typed context, TCB and task stack
 ├── FC03 · Tick, priorities, preemption and time slicing
 ├── FC04 · Delay, blocking, task states and deletion
@@ -79,22 +79,37 @@ FreeRTOS C — 15 cards
 └── FC15 · Integrated deterministic FreeRTOS C application
 ```
 
-## FC01 — Heap schemes and heap_4 block mechanics
+## FC01 — `heap_4`: from a linear cursor to reusable blocks
 
-**Book basis:** 3.1–3.4: `heap_1`–`heap_5`, heap utilities, allocation
+**Duration:** one 30-minute lesson.
-failure and static allocation introduction.
 
+**Direct predecessor:** C07, K&R 5.4 Task04 — `allocbuf[64]`, `allocp`,
+`alloc(5)`, `alloc(7)` and cursor offsets `0 -> 5 -> 12`.
+
+**Book basis:** the `heap_4` and heap-statistics parts of Chapter 3. The other
+FreeRTOS heap implementations are a one-minute map of alternatives, not
+parallel lesson content.
+
+- Opening problem: the linear project cannot release the first 5-byte area
+  while preserving the later 7-byte area, cannot remember reusable holes and
+  recovers the arena only with a whole-arena reset.
+- New model: a block header, an address-ordered free list, first-fit selection,
+  splitting and coalescing of physically adjacent free blocks.
 - Raw API: `pvPortMalloc`, `vPortFree`, `xPortGetFreeHeapSize`,
   `xPortGetMinimumEverFreeHeapSize`, `vPortGetHeapStats`.
-- Main task: compare allocator policies, then walk allocation, split, free
+- Task 1 and Task 2 are short teacher-led models with a student prediction;
-  and coalescing in `heap_4`.
+  they are not separate build/debug sessions during the lesson.
-- Blocks: A1 allocator boundary; A2 block/list layout; A5 allocation flow;
+- Task 3 is the only central student replay: real upstream `heap_4.c`, two
-  A6 free/allocated block state; A7 heap addresses and statistics.
+  stable checkpoints, fragmentation metrics, recovery and OOM.
-- Exercise: predict the free-list shape for a new allocate/free order.
+- Pico 2 W supplies one prebuilt RP2350 hardware observation. `heap_4` is the
-- Hazard3/GDB proof: block headers, aligned sizes and coalesced neighbors
+  allocator selected and linked by the project, not a hardware feature of the
-  agree with the final heap statistics.
+  microcontroller.
-- Main pitfall: treating the minimum-ever-free value as current free space or
+- Acceptance: the student names the three additions over the linear allocator
-  assuming all heap implementations support free/coalescing.
+  (header, free list, coalescing), predicts `2 free blocks -> 1 free block`,
+  and distinguishes current free bytes, largest free block and minimum-ever
+  free bytes.
+- Main pitfall: assuming that a large sum of free bytes guarantees one large
+  allocation, or that minimum-ever-free increases after `free`.
 
 ## FC02 — First task, typed context, TCB and task stack
 
@@ -367,10 +382,12 @@ Every new card must contain:
 8. HTML and TeX generated from one `card_source.json`;
 9. no PDF generation and no commit unless explicitly requested.
 
-## Implementation order
+## Completed implementation order
 
 ```text
-FC03 scheduler
+FC01 heap_4
+→ FC02 first task
+→ FC03 scheduler
 → FC04 state/delay
 → FC05 queues
 → FC06 software timers
@@ -385,5 +402,7 @@ FC03 scheduler
 → FC15 integration
 ```
 
-Ukończenie FC15 jest pierwszą z dwóch bramek wejścia do FreeRTOS C++; drugą
+Obie bramki wejścia do FreeRTOS C++ są spełnione: FC15 zamyka tor systemowy C,
-jest ukończenie właściwych kart językowych C++/OOP.
+a właściwe karty językowe C++/OOP dostarczają model własności, RAII, szablony i
+statyczne trampoline. Następnym etapem jest audyt i realizacja serii FreeRTOS
+C++ karta po karcie, bez mieszania wrapperów z implementacją kernela w C.

plans/informatyka/freertos-cpp.md

@@ -1,14 +1,18 @@
 # FreeRTOS C++ — plan kart
 
-Status: K02 istnieje i jest bieżącą kartą; K03–K16 są planem.
+Status: K02–K16 są gotowe; blok 15 kart jest kompletny. Każda karta ma
+freestanding build C++17, test hosta, kontrolę ABI, wykonanie na Hazard3 oraz
+sprawdzony PDF. Źródła i artefakty używają wspólnej numeracji Kxx/16.
 
 Karta `heap_4` należy do serii FreeRTOS C. FreeRTOS C++ zaczyna się dopiero po
 ukończeniu dwóch torów prowadzonych równolegle: FreeRTOS C oraz C++. K02
-porównuje znany już surowy task C z freestanding wrapperem C++ i Vector V0.
+wprowadza freestanding wrapper `Task<Derived>`, CRTP i statyczny trampoline.
+K03 pokazuje krótki, celowo niepełny Vector V0 bez ukrytego wymagania wykonania
+osobnej karty, a następnie buduje z niego move-only Vector V1 z RAII.
 
 ```text
 FreeRTOS C++
-├── K02 · First Task, Stack, Tick, Scheduler and Vector V0
+├── K02 · C++ Task<Derived> Wrapper, CRTP and Lifecycle
 ├── K03 · Vector V1 — Destructor, Move, Ownership and RAII
 ├── K04 · Scheduler States, Priorities and Typed Ticks
 ├── K05 · C++ Heap Bridge, Heap Models and HeapStats
@@ -32,7 +36,7 @@ freestanding, bez wyjątków, RTTI i zależności od hosted `libstdc++`.
 Każda karta linkuje również do osobnej serii OOP, gdy wrapper rzeczywiście
 realizuje wzorzec lub idiom wymagający osobnego omówienia.
 
-Szczegółowy plan bieżącej K02 oraz kontrolowane porównanie z FC02:
+Materiały wejściowe K02 oraz kontrolowane porównanie z FC02:
 
 - [K02 Task01 — A1–A8 plan](../../../../series/freertos/lab-rv32i-freertos-task-stack-vector/doc/task01-a1-a8-plan.md)
 - [FC02/K02 — paired first-task experiment](freertos-first-task-a1-a8.md)

plans/informatyka/rv32i-asm.md

@@ -1,24 +1,66 @@
 # ASM · RV32I From Blinker to RISC-V
 
-Status: plan, 9 lekcji.
+Status: L01--L09 opracowane, testowane i zarejestrowane; seria zakończona.
 
 ```text
 ASM · RV32I From Blinker to RISC-V
-├── L01 · Number Systems and Storage
+├── L01 · Number Systems and Storage                    [existing · 3 taski]
-├── L02 · FPGA Bring-up and Programming
+├── L02 · FPGA Bring-up and Programming                 [existing · 3 taski]
-├── L03 · Blinker and Synchronous Logic                 [steps 1–3]
+├── L03 · Blinker and Synchronous Logic                 [existing · 3 taski]
-├── L04 · The RISC-V ISA and Instruction Decoder        [steps 4–5]
+├── L04 · The RISC-V ISA and Instruction Decoder        [existing · 3 taski]
-├── L05 · ALU and the Verilog Assembler                  [steps 6–7]
+├── L05 · ALU and the Verilog Assembler                  [existing · 3 taski]
-├── L06 · Control Flow — Jumps and Branches              [steps 8–9]
+├── L06 · Control Flow — Jumps and Branches              [existing · 3 taski]
-├── L07 · Addresses and Memory                           [steps 10–11]
+├── L07 · Addresses and Memory                           [existing · 3 taski]
-├── L08 · Subroutines and the RISC-V ABI                 [steps 13–14]
+├── L08 · Subroutines and ABI                            [existing · 3 taski]
-└── L09 · Load and Store                                 [steps 15–16]
+└── L09 · Load and Store Semantics                       [existing · 3 taski]
 ```
 
 L01 dostarcza języka liczb, kodowania i pamięci. L02 ustanawia fizyczną
 drabinkę FPGA. Kolejne karty prowadzą od logiki synchronicznej do rdzenia,
-który wykonuje podstawowe instrukcje RV32I. Step 12 pozostaje późniejszym
+który wykonuje podstawowe instrukcje RV32I.
-przeglądem jakości implementacji.
+
+## Stan odbioru serii — 2026-07-21
+
+Każda karta ma trzy wykonywalne taski, niezależny model `native-amd64`,
+self-checking SystemVerilog w profilu `hazard3-sim`, akcję debug zapisującą
+VCD, testy kontraktu i stanu, widok React oraz dwustronicowy PDF A4.
+
+| Karta | Dowód końcowy |
+| --- | --- |
+| L01 | systemy pozycyjne, sign/zero extension, shifts i little-endian |
+| L02 | polaryzacja, znany reset, blinker i uporządkowany preflight FPGA |
+| L03 | clock enable, counter blinker i pattern ROM |
+| L04 | dekoder, legalność opcode i bank rejestrów |
+| L05 | ALU, kodowanie instrukcji i wykonanie małego programu |
+| L06 | warunki branch, immediate/target i ślad PC |
+| L07 | LUI/AUIPC, pamięć słów, adres i fault |
+| L08 | JAL/JALR, role ABI i zagnieżdżone powroty |
+| L09 | store strobes, rozszerzenia load i roundtrip pamięci |
+
+Odbiór obejmuje 27 tasków wykonanych w obu profilach: 54/54 zakończyły się
+komunikatem `PASS`. PDF-y przechodzą `qpdf --check`, a ich pliki
+`source-commit.txt` wskazują bezpośredni commit źródłowy.
+
+### Granica sprzętowa L02
+
+Repozytorium L02 nie zgaduje modelu płytki, pinów ani programatora. Dostarcza
+`board/board-contract.yaml` jako bezpieczny szablon oraz osobny formularz
+dowodu fizycznego. Automatyczny preflight i symulacja zawsze raportują
+`hardware_observed=0` oraz `claim=preflight-only`; nie są przedstawiane jako
+zbudowanie bitstreamu ani zaprogramowanie FPGA. Fizyczne zaliczenie wymaga
+konkretnej płytki, SHA-256 bitstreamu, zgodnego device ID, logu konfiguracji i
+zmierzonej obserwacji LED.
+
+### Sposób uruchamiania
+
+```bash
+stemctl series show rv32i-asm
+stemctl list-cards rv32i-asm
+stemctl card use rv32i-asm L01
+stemctl test native-amd64 rv32i-asm L01 1
+stemctl test hazard3-sim rv32i-asm L01 1
+stemctl debug hazard3-sim rv32i-asm L01 3
+```
 
 Materiał źródłowy programu:
 `series/inf/lab-rv32i-c-pointers-arrays/guidelines/year-01-interrupts-to-year-02-freertos.md`.

series/console-bash.json

@@ -0,0 +1,22 @@
+{
+  "id": "console-bash",
+  "title": "Bash · Console Tools",
+  "source_org": "edu-inf",
+  "answer_org": "c2025-1a-inf",
+  "source_remote": "r1",
+  "answer_remote": "r1a",
+  "fallback_branch": "main",
+  "workspace_dir": "console",
+  "source_dir": "console",
+  "default_card": "L01",
+  "cards": [
+    {"id": "L01", "repo": "lab-console-busybox", "branch": "main", "title": "BusyBox — the Swiss Army Knife"},
+    {"id": "L02", "repo": "lab-console-tmux", "branch": "main", "title": "Tmux — sessions, windows and panes"},
+    {"id": "L03", "repo": "lab-console-neovim", "branch": "main", "title": "Neovim — navigation and editing"},
+    {"id": "L04", "repo": "lab-console-git-basics-1", "branch": "main", "title": "Git Basics I — status, add and commit"},
+    {"id": "L05", "repo": "lab-console-git-basics-2", "branch": "main", "title": "Git Basics II — log, diff and restore"},
+    {"id": "L06", "repo": "lab-console-git-branching-1", "branch": "main", "title": "Git Branching I — branch, switch and merge"},
+    {"id": "L07", "repo": "lab-console-git-branching-2", "branch": "main", "title": "Git Branching II — rebase and conflicts"},
+    {"id": "L08", "repo": "lab-console-docker", "branch": "main", "title": "Docker Fundamentals"}
+  ]
+}

series/freertos-c.json

@@ -14,7 +14,7 @@
       "id": "FC01",
       "repo": "lab-rv32i-freertos-heap4",
       "branch": "main",
-      "title": "heap_1–heap_5 and heap_4 mechanics"
+      "title": "heap_4: From Linear Cursor to Reusable Blocks"
     },
     {
       "id": "FC02",
@@ -75,6 +75,30 @@
       "repo": "lab-rv32i-freertos-c-static-allocation",
       "branch": "main",
       "title": "Static Allocation and Bounded Storage"
+    },
+    {
+      "id": "FC12",
+      "repo": "lab-rv32i-freertos-c-diagnostics",
+      "branch": "main",
+      "title": "Assertions, Hooks, Stack Checks and Runtime Diagnostics"
+    },
+    {
+      "id": "FC13",
+      "repo": "lab-rv32i-freertos-c-uart",
+      "branch": "main",
+      "title": "UART Interrupt-to-task Pipeline"
+    },
+    {
+      "id": "FC14",
+      "repo": "lab-rv32i-freertos-c-gpio-timer",
+      "branch": "main",
+      "title": "GPIO, Hardware Timer and Deferred Work"
+    },
+    {
+      "id": "FC15",
+      "repo": "lab-rv32i-freertos-c-integration",
+      "branch": "main",
+      "title": "Integrated Deterministic FreeRTOS C Application"
     }
   ]
 }

series/freertos-cpp.json

@@ -15,6 +15,90 @@
       "repo": "lab-rv32i-freertos-task-stack-vector",
       "branch": "main",
       "title": "C++ Task wrapper: OOP and lifecycle"
+    },
+    {
+      "id": "K03",
+      "repo": "lab-rv32i-freertos-vector-raii",
+      "branch": "main",
+      "title": "Vector V1: destructor, move, ownership and RAII"
+    },
+    {
+      "id": "K04",
+      "repo": "lab-rv32i-freertos-scheduler-states",
+      "branch": "main",
+      "title": "Scheduler states, priorities and typed ticks"
+    },
+    {
+      "id": "K05",
+      "repo": "lab-rv32i-freertos-heap-models",
+      "branch": "main",
+      "title": "C++ heap bridge, heap models and HeapStats"
+    },
+    {
+      "id": "K06",
+      "repo": "lab-rv32i-freertos-allocator-resource",
+      "branch": "main",
+      "title": "MemoryResource and FreeRtosAllocator<T>"
+    },
+    {
+      "id": "K07",
+      "repo": "lab-rv32i-freertos-task-wrapper",
+      "branch": "main",
+      "title": "TaskHandle_t, explicit start and static trampoline"
+    },
+    {
+      "id": "K08",
+      "repo": "lab-rv32i-freertos-static-task",
+      "branch": "main",
+      "title": "DynamicTask, StaticTask, deletion and lifetime"
+    },
+    {
+      "id": "K09",
+      "repo": "lab-rv32i-freertos-kernel-facade",
+      "branch": "main",
+      "title": "Scheduler facade and scoped kernel guards"
+    },
+    {
+      "id": "K10",
+      "repo": "lab-rv32i-freertos-queue",
+      "branch": "main",
+      "title": "Queue<T> and StaticQueue<T, N>"
+    },
+    {
+      "id": "K11",
+      "repo": "lab-rv32i-freertos-mutex",
+      "branch": "main",
+      "title": "Mutex, LockGuard and priority inheritance"
+    },
+    {
+      "id": "K12",
+      "repo": "lab-rv32i-freertos-semaphore-notify",
+      "branch": "main",
+      "title": "Semaphores and task notifications"
+    },
+    {
+      "id": "K13",
+      "repo": "lab-rv32i-freertos-event-group",
+      "branch": "main",
+      "title": "EventGroup and coordinated state"
+    },
+    {
+      "id": "K14",
+      "repo": "lab-rv32i-freertos-sw-timer",
+      "branch": "main",
+      "title": "Software timer and the timer daemon task"
+    },
+    {
+      "id": "K15",
+      "repo": "lab-rv32i-freertos-isr-drivers",
+      "branch": "main",
+      "title": "Explicit FromISR, UART and GPIO wrappers"
+    },
+    {
+      "id": "K16",
+      "repo": "lab-rv32i-freertos-integration",
+      "branch": "main",
+      "title": "Integrated real-time application and evidence"
     }
   ]
 }

series/rv32i-asm.json

@@ -0,0 +1,68 @@
+{
+  "id": "rv32i-asm",
+  "title": "ASM · RV32I From Blinker to RISC-V",
+  "source_org": "edu-inf",
+  "answer_org": "c2025-1a-inf",
+  "source_remote": "r1",
+  "answer_remote": "r1a",
+  "fallback_branch": "main",
+  "workspace_dir": "inf",
+  "source_dir": "inf",
+  "default_card": "L01",
+  "cards": [
+    {
+      "id": "L01",
+      "repo": "lab-rv32i-asm-number-systems",
+      "branch": "main",
+      "title": "Number Systems and Storage"
+    },
+    {
+      "id": "L02",
+      "repo": "lab-rv32i-asm-fpga-bringup",
+      "branch": "main",
+      "title": "FPGA Bring-up and Programming"
+    },
+    {
+      "id": "L03",
+      "repo": "lab-rv32i-asm-blinker",
+      "branch": "main",
+      "title": "Blinker and Synchronous Logic"
+    },
+    {
+      "id": "L04",
+      "repo": "lab-rv32i-asm-decoder",
+      "branch": "main",
+      "title": "The RISC-V ISA and Instruction Decoder"
+    },
+    {
+      "id": "L05",
+      "repo": "lab-rv32i-asm-alu",
+      "branch": "main",
+      "title": "ALU and the Verilog Assembler"
+    },
+    {
+      "id": "L06",
+      "repo": "lab-rv32i-asm-control-flow",
+      "branch": "main",
+      "title": "Control Flow — Jumps and Branches"
+    },
+    {
+      "id": "L07",
+      "repo": "lab-rv32i-asm-addresses-memory",
+      "branch": "main",
+      "title": "Addresses and Memory"
+    },
+    {
+      "id": "L08",
+      "repo": "lab-rv32i-asm-subroutines-abi",
+      "branch": "main",
+      "title": "Subroutines and ABI"
+    },
+    {
+      "id": "L09",
+      "repo": "lab-rv32i-asm-load-store",
+      "branch": "main",
+      "title": "Load and Store Semantics"
+    }
+  ]
+}

workspace.json

@@ -13,7 +13,7 @@
       "title": "Legacy Informatyka series",
       "role": "series",
       "legacy": true,
-      "series": ["inf", "freertos"]
+      "series": ["console-bash", "inf", "rv32i-asm", "freertos"]
     },
     {
       "id": "edu-fiz",
@@ -35,10 +35,18 @@
     }
   ],
   "series": [
+    {
+      "id": "console-bash",
+      "file": "series/console-bash.json"
+    },
     {
       "id": "inf",
       "file": "series/inf.json"
     },
+    {
+      "id": "rv32i-asm",
+      "file": "series/rv32i-asm.json"
+    },
     {
       "id": "fiz",
       "file": "series/fiz.json"