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feat(rv32i-asm): register completed L03-L09 cards

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M. Pabiszczak
2026-07-21 17:28:10 +02:00
parent 6a72fac610
commit ac42d43d5d
4 changed files with 91 additions and 18 deletions
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catalog/rv32i-asm.json
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@@ -5,12 +5,12 @@
"cards": [
{"id": "L01", "repo": "lab-rv32i-asm-number-systems", "number": "01", "title": "Number Systems and Storage", "status": "planned"},
{"id": "L02", "repo": "lab-rv32i-asm-fpga-bringup", "number": "02", "title": "FPGA Bring-up and Programming", "status": "planned"},
{"id": "L03", "repo": "lab-rv32i-asm-blinker", "number": "03", "title": "Blinker and Synchronous Logic", "status": "planned"},
{"id": "L04", "repo": "lab-rv32i-asm-decoder", "number": "04", "title": "The RISC-V ISA and Instruction Decoder", "status": "planned"},
{"id": "L05", "repo": "lab-rv32i-asm-alu", "number": "05", "title": "ALU and the Verilog Assembler", "status": "planned"},
{"id": "L06", "repo": "lab-rv32i-asm-control-flow", "number": "06", "title": "Control Flow — Jumps and Branches", "status": "planned"},
{"id": "L07", "repo": "lab-rv32i-asm-addresses-memory", "number": "07", "title": "Addresses and Memory", "status": "planned"},
{"id": "L08", "repo": "lab-rv32i-asm-subroutines-abi", "number": "08", "title": "Subroutines and the RISC-V ABI", "status": "planned"},
{"id": "L09", "repo": "lab-rv32i-asm-load-store", "number": "09", "title": "Load and Store", "status": "planned"}
{"id": "L03", "repo": "lab-rv32i-asm-blinker", "number": "03", "title": "Blinker and Synchronous Logic", "status": "existing"},
{"id": "L04", "repo": "lab-rv32i-asm-decoder", "number": "04", "title": "The RISC-V ISA and Instruction Decoder", "status": "existing"},
{"id": "L05", "repo": "lab-rv32i-asm-alu", "number": "05", "title": "ALU and the Verilog Assembler", "status": "existing"},
{"id": "L06", "repo": "lab-rv32i-asm-control-flow", "number": "06", "title": "Control Flow — Jumps and Branches", "status": "existing"},
{"id": "L07", "repo": "lab-rv32i-asm-addresses-memory", "number": "07", "title": "Addresses and Memory", "status": "existing"},
{"id": "L08", "repo": "lab-rv32i-asm-subroutines-abi", "number": "08", "title": "Subroutines and ABI", "status": "existing"},
{"id": "L09", "repo": "lab-rv32i-asm-load-store", "number": "09", "title": "Load and Store Semantics", "status": "existing"}
]
}
plans/informatyka/rv32i-asm.md
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# ASM · RV32I From Blinker to RISC-V
Status: plan, 9 lekcji.
Status: L03--L09 opracowane i testowane; L01--L02 pozostają w planie.
```text
ASM · RV32I From Blinker to RISC-V
├── L01 · Number Systems and Storage
├── L02 · FPGA Bring-up and Programming
├── L03 · Blinker and Synchronous Logic [steps 1–3]
├── L04 · The RISC-V ISA and Instruction Decoder [steps 4–5]
├── L05 · ALU and the Verilog Assembler [steps 6–7]
├── L06 · Control Flow — Jumps and Branches [steps 8–9]
├── L07 · Addresses and Memory [steps 10–11]
├── L08 · Subroutines and the RISC-V ABI [steps 13–14]
└── L09 · Load and Store [steps 15–16]
├── L03 · Blinker and Synchronous Logic [existing · 3 taski]
├── L04 · The RISC-V ISA and Instruction Decoder [existing · 3 taski]
├── L05 · ALU and the Verilog Assembler [existing · 3 taski]
├── L06 · Control Flow — Jumps and Branches [existing · 3 taski]
├── L07 · Addresses and Memory [existing · 3 taski]
├── L08 · Subroutines and ABI [existing · 3 taski]
└── L09 · Load and Store Semantics [existing · 3 taski]
```
L01 dostarcza języka liczb, kodowania i pamięci. L02 ustanawia fizyczną
drabinkę FPGA. Kolejne karty prowadzą od logiki synchronicznej do rdzenia,
który wykonuje podstawowe instrukcje RV32I. Step 12 pozostaje późniejszym
przeglądem jakości implementacji.
który wykonuje podstawowe instrukcje RV32I. Karty L03--L09 mają niezależny
model AMD64, self-checking RTL w profilu `hazard3-sim`, artefakt VCD, widok
React oraz dwustronicowy PDF A4. Uruchomienie odbywa się przez `stemctl`.
Materiał źródłowy programu:
`series/inf/lab-rv32i-c-pointers-arrays/guidelines/year-01-interrupts-to-year-02-freertos.md`.
series/rv32i-asm.json
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{
"id": "rv32i-asm",
"title": "ASM · RV32I From Blinker to RISC-V",
"source_org": "edu-inf",
"answer_org": "c2025-1a-inf",
"source_remote": "r1",
"answer_remote": "r1a",
"fallback_branch": "main",
"workspace_dir": "inf",
"source_dir": "inf",
"default_card": "L03",
"cards": [
{
"id": "L01",
"repo": "lab-rv32i-asm-number-systems",
"branch": "main",
"title": "Number Systems and Storage"
},
{
"id": "L02",
"repo": "lab-rv32i-asm-fpga-bringup",
"branch": "main",
"title": "FPGA Bring-up and Programming"
},
{
"id": "L03",
"repo": "lab-rv32i-asm-blinker",
"branch": "main",
"title": "Blinker and Synchronous Logic"
},
{
"id": "L04",
"repo": "lab-rv32i-asm-decoder",
"branch": "main",
"title": "The RISC-V ISA and Instruction Decoder"
},
{
"id": "L05",
"repo": "lab-rv32i-asm-alu",
"branch": "main",
"title": "ALU and the Verilog Assembler"
},
{
"id": "L06",
"repo": "lab-rv32i-asm-control-flow",
"branch": "main",
"title": "Control Flow — Jumps and Branches"
},
{
"id": "L07",
"repo": "lab-rv32i-asm-addresses-memory",
"branch": "main",
"title": "Addresses and Memory"
},
{
"id": "L08",
"repo": "lab-rv32i-asm-subroutines-abi",
"branch": "main",
"title": "Subroutines and ABI"
},
{
"id": "L09",
"repo": "lab-rv32i-asm-load-store",
"branch": "main",
"title": "Load and Store Semantics"
}
]
}
workspace.json
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"title": "Legacy Informatyka series",
"role": "series",
"legacy": true,
"series": ["inf", "freertos"]
"series": ["inf", "rv32i-asm", "freertos"]
},
{
"id": "edu-fiz",
@@ -39,6 +39,10 @@
"id": "inf",
"file": "series/inf.json"
},
{
"id": "rv32i-asm",
"file": "series/rv32i-asm.json"
},
{
"id": "fiz",
"file": "series/fiz.json"