user
22 lines
1.1 KiB
Systemverilog
22 lines
1.1 KiB
Systemverilog
module tb;
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logic clk = 0, rst = 1, write_enable = 0;
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logic [4:0] write_address = 0, read_address1 = 0, read_address2 = 0;
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logic [31:0] write_data = 0, read_data1, read_data2;
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string trace_file;
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register_file dut (.*);
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always #1 clk = ~clk;
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
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repeat (2) @(posedge clk); @(negedge clk); rst = 0;
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write_enable = 1; write_address = 5; write_data = 32'h12345678;
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@(posedge clk); #1; write_enable = 0;
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read_address1 = 5; read_address2 = 0; #1;
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if (read_data1 != 32'h12345678 || read_data2 != 0) $fatal(1, "FAIL task03 first read");
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@(negedge clk); write_enable = 1; write_address = 0; write_data = 32'hffffffff;
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@(posedge clk); #1; write_enable = 0; read_address1 = 0; read_address2 = 5; #1;
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if (read_data1 != 0 || read_data2 != 32'h12345678) $fatal(1, "FAIL task03 x0 or dual read");
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$display("PASS task03 x5=12345678 x0=00000000 dual_read=1");
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$finish;
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end
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endmodule
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