feat(rv32i-asm): register completed L03-L09 cards

2026-07-21 17:28:10 +02:00
parent 6a72fac610
commit ac42d43d5d
4 changed files with 91 additions and 18 deletions
@@ -0,0 +1,68 @@
+{
+  "id": "rv32i-asm",
+  "title": "ASM · RV32I From Blinker to RISC-V",
+  "source_org": "edu-inf",
+  "answer_org": "c2025-1a-inf",
+  "source_remote": "r1",
+  "answer_remote": "r1a",
+  "fallback_branch": "main",
+  "workspace_dir": "inf",
+  "source_dir": "inf",
+  "default_card": "L03",
+  "cards": [
+    {
+      "id": "L01",
+      "repo": "lab-rv32i-asm-number-systems",
+      "branch": "main",
+      "title": "Number Systems and Storage"
+    },
+    {
+      "id": "L02",
+      "repo": "lab-rv32i-asm-fpga-bringup",
+      "branch": "main",
+      "title": "FPGA Bring-up and Programming"
+    },
+    {
+      "id": "L03",
+      "repo": "lab-rv32i-asm-blinker",
+      "branch": "main",
+      "title": "Blinker and Synchronous Logic"
+    },
+    {
+      "id": "L04",
+      "repo": "lab-rv32i-asm-decoder",
+      "branch": "main",
+      "title": "The RISC-V ISA and Instruction Decoder"
+    },
+    {
+      "id": "L05",
+      "repo": "lab-rv32i-asm-alu",
+      "branch": "main",
+      "title": "ALU and the Verilog Assembler"
+    },
+    {
+      "id": "L06",
+      "repo": "lab-rv32i-asm-control-flow",
+      "branch": "main",
+      "title": "Control Flow — Jumps and Branches"
+    },
+    {
+      "id": "L07",
+      "repo": "lab-rv32i-asm-addresses-memory",
+      "branch": "main",
+      "title": "Addresses and Memory"
+    },
+    {
+      "id": "L08",
+      "repo": "lab-rv32i-asm-subroutines-abi",
+      "branch": "main",
+      "title": "Subroutines and ABI"
+    },
+    {
+      "id": "L09",
+      "repo": "lab-rv32i-asm-load-store",
+      "branch": "main",
+      "title": "Load and Store Semantics"
+    }
+  ]
+}