69 lines
1.6 KiB
JSON
69 lines
1.6 KiB
JSON
{
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"id": "rv32i-asm",
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"title": "ASM · RV32I From Blinker to RISC-V",
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"source_org": "edu-inf",
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"answer_org": "c2025-1a-inf",
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"source_remote": "r1",
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"answer_remote": "r1a",
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"fallback_branch": "main",
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"workspace_dir": "inf",
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"source_dir": "inf",
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"default_card": "L03",
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"cards": [
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{
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"id": "L01",
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"repo": "lab-rv32i-asm-number-systems",
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"branch": "main",
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"title": "Number Systems and Storage"
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},
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{
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"id": "L02",
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"repo": "lab-rv32i-asm-fpga-bringup",
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"branch": "main",
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"title": "FPGA Bring-up and Programming"
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},
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{
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"id": "L03",
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"repo": "lab-rv32i-asm-blinker",
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"branch": "main",
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"title": "Blinker and Synchronous Logic"
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},
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{
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"id": "L04",
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"repo": "lab-rv32i-asm-decoder",
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"branch": "main",
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"title": "The RISC-V ISA and Instruction Decoder"
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},
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{
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"id": "L05",
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"repo": "lab-rv32i-asm-alu",
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"branch": "main",
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"title": "ALU and the Verilog Assembler"
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},
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{
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"id": "L06",
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"repo": "lab-rv32i-asm-control-flow",
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"branch": "main",
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"title": "Control Flow — Jumps and Branches"
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},
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{
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"id": "L07",
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"repo": "lab-rv32i-asm-addresses-memory",
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"branch": "main",
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"title": "Addresses and Memory"
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},
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{
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"id": "L08",
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"repo": "lab-rv32i-asm-subroutines-abi",
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"branch": "main",
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"title": "Subroutines and ABI"
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},
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{
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"id": "L09",
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"repo": "lab-rv32i-asm-load-store",
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"branch": "main",
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"title": "Load and Store Semantics"
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}
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]
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}
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